Nanopower, Sub-1 V, CMOS Voltage References With Digitally-Trimmable Temperature Coefficients

Abstract

Two variants of a MOS-only voltage reference are proposed. They are based on MOSFETs operating at a constant inversion level which cancels out nonlinearities of their temperature dependence arising from that of mobility. The theory behind the circuits is thoroughly discussed, a design method is described and experimental results are presented. The two architectures propose different trimming methods for the temperature slope of the references. A test chip was designed and fabricated on a standard 0.35 μm CMOS technology including both architectures. They generate reference voltages around 710 mV, operating from 0.9 V to 3 V supply voltage while consuming 3.0 nA and 3.3 nA. The measured temperature coefficients ranged from 8 to 40 ppm/°C in the -20 °C to 80 °C range.