Publication | Closed Access
A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization
19
Citations
6
References
2004
Year
Unknown Venue
Decision Feedback EqualizationSerial LinksEngineeringMixed-signal Integrated CircuitChannel EqualizationTransceiver CoreComputer EngineeringComputer ArchitectureSystems EngineeringHigh-speed NetworkingSerial Link DesignBack-plane ApplicationsSignal ProcessingOptical Networking
In this paper, a serial link design that is capable of 4.8-6.4 Gbps binary NRZ signaling across 40" of FR4 copper back plane and two connectors is described. The transmitter features a programmable feed forward (FF) equalizer and the receiver uses adaptive decision feedback equalization (DFE) to compensate for the losses in the channel. The transceiver core is built in a 0.13 /spl mu/m standard CMOS technology to be integrated into ASIC chips that require serial links.
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