EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card

Abstract

The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identification (RFID) and smart cards that are energy-efficient and secure against Differential Power Analysis (DPA) attacks. Adiabatic logic is one of the circuit design techniques that can be used to design energy-efficient and secure hardware. However, the existing DPA resistant adiabatic logic families suffer from non-adiabatic energy loss. Therefore, this work presents a novel adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) family that reduces the non-adiabatic energy loss and also is secure against DPA attacks. The proposed EE-SPFAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on EE-SPFAL are used to implement a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that EE-SPFAL based S-box circuit saves up to 65 percent of energy and 90 percent of energy per cycle as compared to the S-box circuit implemented using existing Secured Quasi-Adiabatic Logic (SQAL) and conventional CMOS logic, respectively. Further, the security of EE-SPFAL based S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the EE-SPFAL based S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, we have implemented the one round of Advanced Standard Encryption (AES) algorithm and we found that one round of EE-SPFAL logic based AES consumes uniform current with different input plain texts. Low energy consumption and security against DPA attacks makes EE-SPFAL logic a suitable candidate to implement in IoT devices such as RFID and smart cards.