Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Abstract

Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.