An FPGA based reconfigurable IPSec ESP core suitable for IoT applications

Abstract

This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.