A Multiphase Switched Capacitor Power Amplifier

Abstract

This paper presents an all-digital multiphase switched capacitor power amplifier (MP-SCPA) implemented in a 130-nm CMOS. Quadrature architectures suffer reduced output power and efficiency owing to the combination of out-ofphase signals. The MP architecture reduces the phase difference between the basis vectors that are combined, and hence the output power and efficiency are greatly improved. Sixteen clocks with identical adjacent phase separations are produced by a phase generator with each phase's relative amplitude weighted on the top plate of a capacitor array and combined on a common bottom plate, resulting in linear amplification. The MP-SCPA delivers a peak output power P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 26 dBm with a peak system efficiency (SE) of 24.9%. When amplifying a long-term evolution signal at 1.85 GHz, the average Pout and the SE are 20.9 dBm and 15.2%, respectively, with an Adjacent Channel Leakage Ratio (ACLR) <; -30 dBc and error vector magnitude of 3.5% rms using a 2-D digital predistortion.