Design of Acceptable Stray Inductance Based on Scaling Method for Power Electronics Circuits

Abstract

Recently, high-speed switching circuits using SiC and GaN power devices have been developed for next-generation power electronics circuits and applied to actual traction systems in Japan. Stray inductance caused by the wiring structures between dc capacitors and power devices is one of the most critical parameters that influences high-speed switching circuits. This paper presents a design procedure of acceptable stray inductance for high-speed switching circuits based on a scaling method. It should be noted that the stray inductance is designed for not minimization but optimization, and also is shown not as an absolute value [H] but as a percentage value [%]. By applying the proposed procedure, a maximum stray inductance can be designed for power electronics circuits, considering the switching period, the voltage, and the current ratings of the circuits. To verify the proposed procedure, the experimental results are demonstrated using a SiC-MOSFET and a SiC-Schottky Barrier Diode, with voltage and current ratings of 500 V and 400 A, respectively.