Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

Abstract

Summary In this paper, an efficient and highly accurate algorithm for yield‐aware design of pipeline analog to digital converters (ADCs) based on a four‐step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state‐of‐the‐art MC‐based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10‐bit resolution, 10‐MS/s pipeline analog to digital converter has been simulated in a 0.18‐µm 1.8‐V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright © 2016 John Wiley & Sons, Ltd.