Parallel Sequence Spread Spectrum: Analytical and simulative approach for determination of bit error probability

Abstract

Communication in industrial applications like factory automation (FA) demands very low latency combined with high reliability. Since state of the art wireless technologies are not entirely fulfilling FA requirements, novel approaches are being developed. In this context Parallel Sequence Spread Spectrum (PSSS) is a promising technology, which enables shortest latencies, whereas its bit error performance has not yet been analyzed. Similar to Direct Sequence Spread Spectrum (DSSS), where data symbols are spread each with an appropriate sequence, PSSS spreading is performed based on a cyclically shifted m-sequence. Each cyclic shift of the base m-sequence is code, which enables a CDMA scheme. This paper deduces a theoretical and simulative approach determining the bit error performance for an ideal CDMA and for a time offset between several nodes in an AWGN channel. Based on this analysis, performance constraints and reliability limits such as requested synchronization accuracy are revealed.