A fast systolic priority queue architecture for a flow-based Traffic Manager

Abstract

This paper presents a fast systolic priority queue architecture usable in a traffic manager. The purpose of the traffic manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G wireless standards. The proposed hardware architecture of the systolic priority queue enables pipelined en/dequeue operations at constant time rate. Detailed description of this processing module is provided, together with the associated algorithm, and the architecture of the traffic manager. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. The obtained results are compared across a range of priority queue depths and performance metrics with existing approaches. A throughput improvement of 44% is claimed over best previously reported results. The proposed design of the traffic manager works at 118 MHz when implemented on a Kintex-7 FPGA from Xilinx.