Design fast round robin scheduler in FPGA

Abstract

As a classical scheduling algorithm, the round robin scheduling algorithm is as widely used at present as it was in the past. A new FPGA-based implementation method is presented in this paper. After considering the FPGA structural characteristics and requirements of the system, a method using a pipelined priority encoder (PPE) and a barrel shifter (BS) is implemented effectively in an FPGA, and the performance of the PPE and BS is evaluated. The test results of the system show that the algorithm implementation is successful and fulfills the system requirements. At the same time, the method is also useful in other cases in which the round robin is applied.