Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node trench SPT DRAM cell and CMOS logic technology

Abstract

A comprehensive study of design point constraints on n-well and epitaxial design for a CMOS trench DRAM/SRAM/logic process is presented. Design criteria and guidelines, derived from experimentation and process/device simulation, are based on the following considerations: trench DRAM storage node capacitance, DRAM leakage mechanisms, retention time, n-well electrical parametrics, pnp bipolar current gain, latchup, and electrostatic discharge (ESD) performance. The methodology is discussed for achieving optimum power, signal, retention time, performance, reliability and ESD performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>