Hardware-backpropagation learning of neuron MOS neural networks

Abstract

This paper describes the design and architecture of a neural network having a hardware-learning capability, in which a functional transistor called neuron MOSFET (neuMOS or vMOS) is utilized as a key element. In order to implement learning algorithm on the chip, a new hardware-oriented backpropagation learning algorithm has been developed by modifying and simplifying the original backpropagation algorithm. In addition, a six-transistor synapse cell which is free from standby power dissipation and is capable of representing both positive and negative weights (excitatory and inhibitory synapse functions) under a single 5 V power supply has been developed for use on a self-learning chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>