A high performance epitaxial SiGe-base ECL BiCMOS technology

Abstract

In this work we present a high speed, self-aligned SiGe epitaxial-base ECL BiCMOS technology in which we achieved a record 18.9 ps ECL gate delay at 7.7 mW, 59 GHz peak f/sub max/, 50 GHz peak f/sub T/, and 0.25 mu m-channel CMOS devices with transconductances of 240 mS/mm for the nFET and 140 mS/mm for the pFET. Key technology features include a dielectric-filled deep and shallow trench isolation, a polysilicon-emitter SiGe-epitaxial-base NPN, a low-thermal-cycle 0.25 mu m-channel CMOS, a self-aligned silicide on extrinsic base and Source/Drain/Gate, a thin Ti/W local interconnect combined with two metal levels of AlCu, a nitride/oxide decoupling capacitor, and polysilicon resistors. This BiCMOS process is the highest level of integration and performance yet achieved in a SiGe-base technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>