Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

Abstract

A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.