A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique

Abstract

This paper presents a versatile multimedia functional unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the spurious power suppression technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18 mum/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.