A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

Abstract

A double polysilicon bipolar technology with high-speed, high-packing density, low power consumption, and high alpha -particle immunity has been newly developed. Bonded SOI substrates are used to improve the alpha -particle immunity, and scaled CMOS memory cells are introduced to reduce the power consumption and to increase the packing density. The cut-off frequency of the bipolar transistors is as high as 27 GHz and the area of the CMOS memory cell is 58 mu m/sup 2/. This technology is promising for application to ultra high-speed, high-density LSIs with ECL-CMOS scheme.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>