MPSoC power estimation framework at transaction level modeling

Abstract

Early power estimation is increasingly important in multiprocessor system-on-chip (MPSoC) architectures for a reliable design space exploration (DSE). In this paper, we present an MPSoC power modeling framework at the timed programmer view (PVT) level that offers a good performance/power tradeoff to be found early in the design flow. Using a hybrid power modeling methodology, we developed several power models derived from both physical measurements and analytical expressions. Plugging these power models into the PVT architectural simulator makes it easy to estimate the application's performance and power consumption with high simulation speedup. The effectiveness of our method is illustrated through a DSE for a parallelized version of H.263 encoder application.