Complementary III-V heterostructure FETs for low power integrated circuits

Abstract

The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (AlGa)As barrier layer. A 1024*1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>