A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator

Abstract

This paper presents a novel noise shaping SAR architecture that is simple, robust and low power. It is fully passive and only needs minor modification to a conventional SAR ADC. Through a passive integrator, quantization noise, comparator noise and DAC noise are shaped with a noise transfer function of (1 - 0.75z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ). Unlike conventional multi-bit delta-sigma ADCs, both the noise transfer function and the error transfer function of DAC mismatches are immune to process-voltage-temperature variations. A prototype chip is fabricated in a 0.13μm CMOS process. At 1.2V and 2MS/s, the chip consumes 61μW power. SNDR increases by 6dB and the Schreier FoM increases by 3dB with OSR doubled. At an OSR of 8, SNDR is 74dB and the Schreier FoM is 167dB.