A 1-V low-power high-performance 32-bit conditional sum adder

Abstract

A 32-bit conditional sum adder has been designed using a 0.5-/spl mu/m CMOS process with V/sub th/=0.2 V for 1-V operation. The simulated delay and power dissipation (at 30 MHz) are 9.8 ns and 310 /spl mu/W, respectively, as extracted from layout. The standby power is /spl sim/4 /spl mu/W. As a comparison, the same adder has a 5 ns delay, consuming 4.5 mW, if implemented on a standard 3V-process.