Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits

Abstract

Signed-digit (SD) arithmetic exploits positive and negative digits requiring more than two states. It is long known that an addition using trits, i.e. each digit stores not only a 0 or a 1 but also either 2 or -1, requires only a constant number of steps independent of the operands' word length. However, current processors could not profit from that due to the lack of fast, dense and CMOS compatible memory cells that can store reliably multiple states. Memristors offer these features making it necessary to re-evaluate different SD number representations and to evaluate the consequences of an implementation of a multi-value register file with memristors concerning latency, area and energy consumption.