A SV-UVM framework for Verification of SGMII IP core with reusable AXI to WB Bridge UVC

Abstract

Exponential advancement in technology has led to the development of complex digital systems, which has made them more error prone. Conventional verification techniques lacks flexibility of verification environment and are inefficient to balance between market demands and time to market. Universal Verification Methodology (UVM), a System Verilog (SV) based methodology helps to create robust and reusable verification environment. In this work, we present an efficient SV-UVM framework for the verification of Serial Gigabit Media Independent Interface (SGMII) IP core, a single lane 1.25 Gbps data rate interface between Ethernet Media Access Control (MAC) and Physical (PHY) layer. The core has an AMBA AXI (Advanced eXtensible Interface) master interface to access the register space of the IP. UVM Verification Component (UVC) of AXI to WB (Wishbone) bridge is reused in the verification of SGMII core for the configuration of several registers in the core which is WB compatible. All simulations are done in NCsim and waveforms are analysed using Simvision. The coverage analysis is done using Incisive Metrics Center (IMC).