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A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS
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2016
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Low-power ElectronicsTi Sar AdcElectrical EngineeringSar AdcEngineering16-Nm CmosCalibrationData ConverterMixed-signal Integrated CircuitAnalog DesignComputer EngineeringBackground Timing-skew CalibrationInstrumentationPower ElectronicsMicroelectronicsTiming-skew CalibrationAnalog-to-digital Converter
This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.