Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D⁺IC

Abstract

A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> IC connected by high density interconnect. The photocurrent of the monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> <;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> IC enables the low power and low cost monolithic 3D image sensor.