A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC

Abstract

A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.