A 24.7 mW 65 nm CMOS SAR-Assisted CT $\Delta\Sigma $ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR

Abstract

A continuous-time (CT) sixth-order ΔΣ modulator, employing a 4 bit asynchronous successive-approximation-register (ASAR) quantizer, incorporates second-order noise coupling (NC) and excess-loop-delay compensation, all are tightly integrated into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). The mixed-mode second-order NC structure is implemented in both discrete-time (DT) and CT domains. Clocked at 900 MHz, the 65 nm CMOS prototype measures a 120 dB/decade shaped noise slope and a peak 75.3 dB SNDR at an over-sampling ratio (OSR) of 10, yielding a Schreier FoM of 167.9 dB and a Walden FoM of 57.7 fJ/conversion-step. The modulator occupies an active area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 24.7 mW.