A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS

Abstract

This brief presents a 0.3-V energy-efficient 10-bit successive approximation register analog-to-digital converter. A shifted monotonic switching procedure is proposed to achieve an average digital-to-analog converter switching energy of 63.75 CV2. Two redundant bits are implemented with error tolerance of ±12 mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in a 90-nm CMOS with a core size of 250 μm × 50 μm (0.0125 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). At 250 KS/s and Nyquist rate input, it consumes 52.3 nW at 0.3-V supply with an achieved signal-to-noise-and-distortion ratio of 51.21 dB and a resulting figure of merit of 0.705 fJ/conv.-step.