A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets

Abstract

In this paper, a highly reliable radiation hardened by design memory cell (RHD12) using 12 transistors in a 65-nm CMOS commercial technology is proposed. Combining with layout-level design, the TCAD mixed-mode simulation results indicate that the RHD12 not only can fully tolerant the single-event upset occurring on any one of its single nodes but can also tolerant single-event multiple-node upsets in a single memory cell, which are caused by charge sharing. Moreover, a set of HSPICE post-simulations are done to evaluate the RHD12 and other state-of-the-art memory cells, which show that our proposed memory cell has better performance, considering the area, power consumption, and access time.