Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

Abstract

Planar copper interconnects suffer from surface roughness that results in performance degradation. This paper presents a novel analytical model for calculation effective resistivity and mean free path in on-chip copper interconnects. The closed form expressions are obtained from a generalized surface and grain boundary scattering approach that is combined with Mandelbrot-Weierstrass (MW) fractal function. It is observed that resistivity increases while mean free path reduces significantly for rough on-chip interconnects when compared with that of smooth lines. Current and future technology nodes i.e., 45 nm, 22 nm, 13 nm and 7 nm are considered for our analysis. The analytical models are validated against industry standard field solvers Ansys Q3D Extractor and previous data available in literature that exhibit excellent accuracy. Finally, we also present computational overhead in terms of simulation time, matrix size, number of tetrahedrons and memory for different values of roughness and technology nodes.