A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS

Abstract

A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.