A new hardware architecture for operations in GF(2/sup n/)

Abstract

The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconventional basis and present a new bit-parallel multiplier which is as efficient as the modified Massey-Omura multiplier using the type I optimal normal basis.