CMOS Sensor Nodes with Sub-PicoWatt TFET Memory

Abstract

This paper describes the applicability of tunnel FETs (TFET) to ultra-low-power sensor-node embedded static random-access memories (SRAMs). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a five orders of magnitude reduction in standby current. A lookup table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V or lower. The read and write static noise margins are evaluated at 120 and 200 mV, with the operation speeds of 3.8 GHz and 800 MHz at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V in read and write, respectively. The cell leakage is less than 5 fA at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V. A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 4 fW/cell or 4.1 pW for a 1-kb array at 1 V supply voltage.