IEEE Transactions on Circuits and Systems I Regular Papers · 2016 · 27 citations · 32 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Integrated Circuits
A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Furthermore, a 2.8-bit SAR conversion embedded in the 1st stage also improves the speed and downsizes the required decoupling capacitance of reference voltage. With the foreground calibration, the inter-stage DAC error and gain/offset errors between interleaving channels are resolved. The proposed ADC, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at low input frequencies and 60.1 dB near Nyquist rate. The prototype occupies an active area of 0.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the corresponding FoM is 30.3 fJ/conversion-step.
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