A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM

Abstract

An area-efficient, time-domain folding ADC achieves a 10 GS/s conversion speed and a 6 bit resolution in 65 nm CMOS. The natural time-domain folding effect of the ring oscillator (RO) leads to an inherently linear and compact folding operation. The single front-end voltage-to-time converter (VTC) running at the full conversion speed obviates any input buffer or clock-skew calibration often needed in large arrays of time-interleaved (TI) ADCs. The converter back-end consists of a four-way TI, RO-based time-to-digital converter (TDC) array with inherent dynamic element matching (DEM) that achieves high conversion speed and good linearity simultaneously. The prototype ADC was fabricated in a 65 nm CMOS process with an active area of only 0.073 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Thanks to the built-in DEM, the measured DNL and INL are +0.27/-0.28 LSBs and +0.48/-0.49 LSBs, respectively. The measured SFDR and SNDR are over 42 dB and 27 dB with a Nyquist input at 10 GS/s.