A 0.45 V 100-Channel Neural-Recording IC With Sub-<formula formulatype="inline"><tex Notation="TeX">$\mu {\rm W}$</tex></formula>/Channel Consumption in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS

Abstract

Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In this paper, a neural recording architecture with dynamic range folding and current reuse techniques is proposed and dedicated to solving the noise and dynamic range trade-off under low voltage low power operation. Measured results from the silicon prototype show that the proposed design achieves 3.2 μVrms input referred noise and 8.27 effective number of bits at only 0.45 V supply and 0.94 μW/channel power consumption.