Transformer-Based Tunable Matching Network Design Techniques in 40-nm CMOS

Abstract

A fully integrated transformer-based tunable impedance-matching network is described. The tuning network independently tunes the real and imaginary parts of the impedance. A test chip implemented in a 40-nm CMOS process achieves the resistive tuning range of one octave, making it suitable for shared Bluetooth/Wi-Fi power amplifier (PA) applications. The main sources of insertion loss are identified, and strategies to minimize the insertion loss while maximizing the tuning range of the real and imaginary parts are discussed in this brief.