International Journal of Computer Theory and Engineering · 2013 · 11 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysLow-power DesignDigital Signal ProcessingDynamic Power ReductionField-programmable Gate Array ArchitectureFpga ArchitectureLow-power Digital Circuit DesignLow-power Fpga DesignDigital Signal Processing BlocksGlitch Power ReductionLow-power MultipliersLow-power Signal ProcessingMultiplexer DesignMultiplier DesignPower ConsumptionPower Consumption Optimization
In this paper, the authors present implementation of a low power and low area digital Finite Impulse Response (FIR) filter. The we method for reduce dynamic power consumption of a digital FIR filter is use of low power multiplexer based on shift/add multiplier without clock pulse and we applied it to fir filter until power consumption reduced thus reduce power consumption due to glitching is also reduced. The minimum power achieved is 56mw in fir filter based on shift/add multiplier in 100MHZ with 8bits inputs and 8bits coefficients. The proposed FIR filter was synthesized implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device xc4vlx200 also power is analized using Xilinx XPower analyzer.
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FPGA Implementation of High Speed FIR Filters Using Add and Shift Method
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design · 2006 · 98 citations
Engineering, Computer Engineering, Electrical Engineering +17