n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (I L )which vary from wafer to wafer, typicaily from 10 ^-11 to 10 ^-7 A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10 ^-11 ∼ 10 ^-10 A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al 2 O 3 -Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of I L , which support the general conclusions of the model, are presented. I L is shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of I L is the state of the Al 2 O 3 -Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10 ^-9 A/mil of gate width.

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