Implementation of a Direct Sequence Spread Spectrum Baseband Transmitter Using Silicon Nanowire Technology

Abstract

This study presents silicon nanowire implementation of a Direct Sequence Spread Spectrum (DSSS) baseband transmitter where its circuit performance, power consumption and layout issues are examined and compared with earlier studies. The baseband transmitter contains an 8-Phase Shift Keying (8-PSK) modulator, a 4th order PN generator, a binary bit mapper and two bit multipliers. It generates chips at a rate of 28.6 GChips/sec. The average power consumption is 198.5 μW at 1.9 GHz symbol clock frequency; the instantaneous power consumption changes between 188.1 μW and 213.4 μW depending on the processed symbol. With these bit rate and power consumption figures, the transmitter is ideal for any hand-held wireless device application. The worst-case critical data-path delay is 31 ps; after parasitic RC extraction, this results in a 28.6 GHz chip clock frequency for the transmitter. The transmitter layout uses fabric-matrix approach where NMOS and PMOS transistors are placed alternatively on a SOI substrate and occupies approximately 2.1 μm 2 of chip area.