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Tuning On–Off Current Ratio and Field-Effect Mobility in a MoS<sub>2</sub>–Graphene Heterostructure <i>via</i> Schottky Barrier Modulation
269
Citations
41
References
2014
Year
EngineeringOn–off Current RatioGraphene NanomeshesGraphene ExhibitsNanoelectronicsQuantum MaterialsField-effect MobilityOxide HeterostructuresElectrical EngineeringPhysicsElectron TransportGraphene Quantum DotElectronic MaterialsField-effect TransistorCondensed Matter PhysicsApplied PhysicsGrapheneGraphene NanoribbonOptoelectronics
Field-effect transistor (FET) devices composed of a MoS2-graphene heterostructure can combine the advantages of high carrier mobility in graphene with the permanent band gap of MoS2 for digital applications. Herein, we investigate the electron transfer, photoluminescence, and gate-controlled carrier transport in such a heterostructure. We show that the junction is a Schottky barrier, whose height can be artificially controlled by gating or doping graphene. When the applied gate voltage (or the doping level) is zero, the photoexcited electron-hole pairs in monolayer MoS2 can be split by the heterojunction, significantly reducing the photoluminescence. By applying negative gate voltage (or p-doping) in graphene, the interlayer impedance formed between MoS2 and graphene exhibits an 100-fold increase. For the first time, we show that the gate-controlled interlayer Schottky impedance can be utilized to modulate carrier transport in graphene, significantly depleting the hole transport, but preserving the electron transport. Accordingly, we demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics. In the NMOS digital regime, we report a very high room temperature on/off current ratio (ION/IOFF ∼ 36) in comparison to graphene-based FET devices without sacrificing the field-effect electron mobilities in graphene. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered. The device architecture presented here may enable semiconducting behavior in graphene for digital and analogue electronics.
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