Nano Letters · 2016 · 545 citations · 40 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsCarrier TransportQuantum TunnelingSemiconductor Device MaterialsSemiconductor HeterostructuresSemiconductor InterfacesSemiconductor PhysicsCharge Carrier DensityDifferential ResistanceHeterojunction DevicesHeterojunctionsHeterostructure TransistorsInterlayer CouplingTransconductanceTunnel Diodes
The study investigates band‑to‑band tunneling in both transverse and lateral directions of MoS₂/WSe₂ van der Waals heterojunctions. Strong interlayer coupling between MoS₂ and WSe₂ layers induces charge‑density and band‑modulation effects that drive the observed tunneling behavior. At room temperature the heterojunction diode exhibits negative differential resistance with an average conductance slope of 75 mV/dec and a curvature coefficient of 62 V⁻¹, while the induced transconductance reversal enables a multivalued logic inverter that achieves three distinct logic levels using a single pair of p‑type transistors.
This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temperature negative differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an average conductance slope of 75 mV/dec with a high curvature coefficient of 62 V–1. Associated with the tunnel-diode characteristics, a positive-to-negative transconductance in the MoS2/WSe2 heterojunction transistors is observed. The transition is induced by strong interlayer coupling between the films, which results in charge density and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.
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