A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions

Abstract

High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation at the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to reduce the number of transitions on FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT solvers thatconducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient betweentransitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.