A cost model analysis comparing via-middle and via-last TSV processes

Abstract

Cost remains a key factor for implementation of Through Silicon Via (TSV) in high-volume manufacturing. As compared to via-first and via-middle TSV, via-last (from wafer back-side) TSV possesses the advantage of a more simple process flow and more flexibility in integration for more varied applications. Previously, a cost model analysis for Through-Silicon-Interposer (TSI) using via-first TSV has been presented [1]. In this paper, we will apply a similar model to analyse and compare the fabrication cost for our current via-last and via-middle process flow. A CMP-based via-last process flow is used as a reference baseline in this study. This process flow follows that of a conventional via-middle TSV, but differs mainly in the absence of a TSV backside reveal process. Based on our analysis results, our baseline via-last TSV flow shows ~10% cost reduction when compared to via-middle TSV. We further explored an alternative via-last process flow (combining TSV and RDL into a single plating step) as reported in [2] for a further 10% reduction in cost.