15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS

Abstract

Technology advancement has recently made it attractive to replace the flash quantizer (QTZ) in a multibit ΔΣ modulator by an asynchronous successive-approximation-register (ASAR) QTZ to improve the overall power efficiency [1]. However, limited by the SAR throughput, most works in this regime report only a small signal bandwidth. To achieve a wide bandwidth, a lower oversampling ratio (OSR) can be utilized, which dictates more aggressive noise shaping for a constant SNDR, and thus can potentially compromise the stability of the modulator. A discrete-time (DT) noise-coupling (NC) technique [2] circumvents this problem and is suitable for deployment in an SAR-assisted multibit ΔΣ modulator. In a switched-capacitor SAR, the quantization error (Eq) is naturally produced on the summing node at the end of the SAR bit cycles and can be buffered and injected back into the loop filter (LF) to facilitate NC. In addition, the switched-capacitor SAR DAC also provides a convenient means to incorporate the excess-loop-delay (ELD) compensation in a continuous-time (CT) modulator. To explore these techniques, this paper presents a 10× OSR, 4th-order CT ΔΣ modulator with mixed-mode (DT-CT) 2nd-order NC and ELD compensation, all integrated in a 4b ASAR QTZ.