Publication | Closed Access
14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems
139
Citations
5
References
2016
Year
Unknown Venue
Off-chip Memory AccessesConvolutional Neural NetworkDeep Neural NetworksKernel Data CompressionMachine LearningEngineeringHardware AccelerationIntelligent Ioe SystemsComputer EngineeringComputer ArchitectureDomain-specific AcceleratorComputer ScienceEnergy-efficient Cnn ProcessorParallel ComputingDeep LearningNeural Architecture SearchModel Compression
In this paper, we present an energy-efficient CNN processor with 4 key features: (1) a CNN-optimized neuron processing engine (NPE), (2) a dual-range multiplyaccumulate (DRMAC) block for low-power convolution operations, (3) an on-chip memory architecture and a utilization scheme for reducing off-chip memory accesses, (4) kernel data compression for further reducing off-chip memory accesses.
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