Publication | Open Access

Anytime system level verification via parallel random exhaustive hardware in the loop simulation

Hardware ModelingEngineeringHardware-in-the-loop SimulationHardware Verification LanguageRuntime VerificationVerificationComputer EngineeringFormal MethodsSystems EngineeringComputer ArchitectureComputer-aided VerificationParallel ProgrammingComputer ScienceParallel ComputingLoop SimulationFormal VerificationHardware Verification