S/sup 2/I: a two-step approach to switched-currents

Abstract

The principal causes of nonideal behavior which degrade precision and linearity in switched-current circuits, and the circuit techniques which are frequently applied to suppress them, are reviewed. These techniques include the use of negative feedback to reduce errors resulting from channel-length modulation and capacitive feedback, and fully-differential circuits with charge cancellation to reduce switch charge injection. It is argued that this piecemeal application of circuit techniques to suppress individual errors frequently carries penalties for silicon area, power dissipation, bandwidth and low supply voltage operation. An alternative approach is presented which attempts to enhance basic cell performance through successive refinement of the memorized sample. This is achieved in a two-step technique, called S/sup 2/ I, in which the input sample is coarsely memorized, a process which introduces a combination of all the normal errors, followed by detection and suppression of the combined errors. The circuit solution requires the addition to the basic memory cell of only two extra switches. The new cell carries little or none of the aforementioned penalties.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>