Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique

Abstract

In this brief, a new write assist technique is proposed to improve the write characteristics of 1T-1 magnetic tunnel junction (MTJ) spin-torque transfer memory bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write 1 operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65-nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared with the boosted wordline (BWL) technique. In addition, the proposed write assist technique leads to 12% and 48% bitcell area reduction compared with BWL and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with BWL and balanced write techniques, respectively.