VeriTrust: Verification for Hardware Trust

TLDR

Today's integrated circuit designs are vulnerable to hardware Trojans that act as backdoors, potentially causing functionality changes, data leaks, or denial of service. The paper proposes VeriTrust, a verification technique to detect hardware Trojans inserted during design. VeriTrust automatically identifies potential HT trigger inputs by examining verification corners, leveraging that HTs are activated by dedicated trigger inputs not sensitized by test cases, and is insensitive to implementation style. Experimental results show that VeriTrust detects all evaluated HTs, constructed from various design methodologies, with moderate extra verification time.

Abstract

Today's integrated circuit designs are vulnerable to a wide range of malicious alterations, namely hardware Trojans (HTs). HTs serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or denial of service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques based on “unused circuit identification” is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in this paper) at the cost of moderate extra verification time.